`timescale 1ns/1ns

module triffic_light(
           input clk,
           input rst_n,
           input pass_request,
           output wire [7: 0] clock,
           output reg red,
           output reg yellow,
           output reg green
       );

parameter idle = 4'd0;
parameter s1 = 4'd1;
parameter s2 = 4'd2;
parameter s3 = 4'd3;
reg [3: 0] state;
reg [3: 0] next_state;
reg [6: 0] cnt;
always@(posedge clk or negedge rst_n)
	begin
		if (!rst_n)
			state <= idle;
		else
			state <= next_state;
	end


always@( * )
	begin
		if (!rst_n)
			next_state <= idle;
		else
			case (state)
				idle:
					begin
						next_state <= s1;
					end
				s1:
					begin
						if (cnt == 'd0)
							next_state <= s2;
						else
							next_state <= s1;
					end
				s2:
					begin
						if (cnt == 'd0)
							next_state <= s3;
						else
							next_state <= s2;
					end
				s3:
					begin
						if (cnt == 'd0)
							next_state <= s1;
						else
							next_state <= s3;
					end
				default:
					next_state <= state;
			endcase
	end

always@(posedge clk or negedge rst_n)
	begin
		if (!rst_n)
			begin
				red <= 1'b0;
				yellow <= 1'b0;
				green <= 1'b0;
			end
		else if (state == s1)
			begin
				red <= 1'b0;
				yellow <= 1'b0;
				green <= 1'b1;
			end
		else if (state == s2)
			begin
				red <= 1'b0;
				yellow <= 1'b1;
				green <= 1'b0;
			end
		else if (state == s3)
			begin
				red <= 1'b1;
				yellow <= 1'b0;
				green <= 1'b0;
			end
	end

always@(posedge clk or negedge rst_n)
	begin
		if (!rst_n)
			cnt <= 'd0;
		else if (state == idle && next_state <= s1)
			cnt <= 7'd60;
		else if (state == s1 && pass_request && (cnt > 7'd10))
			cnt <= 7'd10;
		else if (state == s1 && next_state <= s2)
			cnt <= 7'd5;
		else if (state == s2 && next_state <= s3)
			cnt <= 7'd10;
		else
			cnt <= cnt - 1'b1;
	end

endmodule
